A transistor using a ferroelectric for its gate insulator film which allows data storage and data reading and writing to be conducted by the single transistor is expected to be a highly integrated memory in the next generation. Transistors of this type have their electrical conduction controlled corresponding to directions of the electric polarization of a ferroelectric. While their prototype is an MFS transistor having an MFS (metal, ferroelectric and semiconductor) laminated structure, a structure is also being investigated in which so that both characteristics of the semiconductor and ferroelectric may not be impaired; a buffer insulator is interposed between them (see, Patent References 1 and 2). Transistors having this structure are known as a MFIS (metal, ferroelectric, insulator and semiconductor) transistor.
The MFS and MFIS transistors are each expected in principle to possess features that (1) the use of electric polarization causes data not to disappear if power supply is switched off; (2) reading can be operated only by seeing electrical conduction between source and drain electrodes of the transistor and data are not destructed in content after the reading operation; and (3) both data reading and writing speeds are high as is the DRAM.
Conventional MFS and MFIS transistors have had the problem, however, that data written on them when seen to operate as a memory transistor do disappear in one day at the longest after writing (see Non-patent References 1 and 2).
To with, for those conventional MFS and MFIS transistors it was not possible to retain data for a term which their implementation requires. This is believed to be mainly due to large leakage currents through the buffer layer and ferroelectric, causing charges to store in the vicinity of an interface between the ferroelectric and buffer layer and the charges to shield electric polarization in the ferroelectric, and making it impossible to control electrical conduction of channels of the transistor by means of their electric polarization.
The problem also arises that a voltage needed for application to the MFS or MFIS when writing data on the ferroelectric tends to be mostly applied to the buffer layer if its dielectric constant is low.
Thus, the present inventors have proposed in Patent References 3 and 4 an MFS or MFIS transistor, i.e., a semiconductor ferroelectric device, which can practically be implemented with the ability to hold a data for a certain extent of term, as well as a method of making the device.
In Patent Reference 3 there is provided a memory transistor whose data storage term is indeed sufficiently long and in which the insulator buffer layer is composed of Hf1−XAl2XO2+X+Y or Hf2+u doped with nitrogen to allow the leakage currents across both the insulator buffer layer and ferroelectric to be held low.
In Patent Reference 4 there is provided a method of making a semiconductor ferroelectric memory device having a transistor in which an insulator buffer layer mainly constituted of hafnium oxide, a ferroelectric and a gate electrode are laminated in this order on a semiconductor substrate or semiconductor area having a source and a drain region, the method including the steps of a semiconductor surface treatment, forming the insulator buffer layer, forming a layer of the ferroelectric, forming the gate electrode and a heat treatment and being characterized in that the said step of forming the insulator buffer layer is carried out in a gaseous atmosphere having nitrogen and oxygen mixed together at a molar ratio ranging between 1:1 and 1:10−7.
While the ferroelectric of such MFS and MFIS transistors have often been constituted using a ferroelectric mainly composed of an STB such as Sr—Bi—Ta—O that is an oxide of strontium Sr, bismuth Bi and tantalum Ta, in an MFS or MFIS transistor being developed so as to be finer or smaller a demand has also come to arise that the gate electrode in length and the ferroelectric film in thickness be further reduced.
The present inventors have focused their efforts on the study of MFIS transistors having a wide memory window even if the ferroelectric has a thickness of 200 nm or less, and made it known in Patent and Non-Patent References 3 and 5 to provide a MFS or MFIS transistor suitably using a ferroelectric whose main component is an SCBT that is an oxide of strontium Sr, calcium Ca, bismuth Bi and tantalum Ta, such as Sr—Bi—Ta—O. As an example of development of the fine ferroelectric device an MFIS transistor having a gate length of 260 nm using an SBT ferroelectric has been made known (see Non-patent Reference 4).
Also in the MFS or MFIS transistor, it is mentioned that covering its gate stack with a buildup of the ferroelectric layer or the buffer and ferroelectric layers widens the memory window, the buildup also serving as a side face protective layer (see Patent Reference 6).